Commit Graph
27 Commits
Author SHA1 Message Date
Salvatore Sanfilippo a04f46fa42 DeepSeek v4.1 Flash support for CUDA
Add bounded SSD streaming, exact short prefills, accelerated large prefills, and native session batching. Support resident tensor parallel inference across two DGX Sparks over RoCE, with aligned expert shards, split vocabulary projection, decode graphs, and shared-expert overlap.

Include primitive, state, transport, and model regression tests, plus usage documentation and measured QA results.
2026-09-13 17:32:48 +02:00
Salvatore Sanfilippo 49ec955c8c Keep ROCm QA builds clean for partial tiles and CPU-only fixtures
Do not force full unrolling of runtime-bounded IQ2 tail loads. Keep the ROCm graph memory-baseline initialization out of DS4_NO_GPU builds, matching the declaration and allowing the model-free session-state suite to compile.
2026-09-06 23:41:42 +02:00
Salvatore Sanfilippo 909d6560cb Merge PR #992: ROCm gfx1151 prefill and DSpark improvements
Preserve all five original commits by Donato Capitella. Resolve the DSpark fallback conflict by retaining the existing Metal/DGX Spark short-proposal behavior and adding the ROCm reference-alignment condition.

Closes #992
2026-09-06 22:58:22 +02:00
Donato Capitella 64e490bc1a rocm: specialize gfx1151 IQ2 prefill input staging
Use direct input loads for full IQ2_XXS tiles with width at least 32 on HIP/gfx1151. For partial tiles, initialize the invalid suffix once and reload only the valid prefix at each K stage. Preserve scratch lifetime, barriers and invalid-tail handling; other backend and quantization templates retain their existing path.

Keep small IQ2 and Q2_K templates on their established masked-load path, where the wider load-scheduling change altered compiler accumulation order during development. The specialization changes input staging without changing the selected matrix operations or their source-level accumulation.
2026-09-06 11:01:25 +01:00
Salvatore Sanfilippo 45f54e9d11 Use aligned expert vector kernels for small Spark batches
Reuse the existing fused IQ2 gate/up and Q2 down paths for up to eight resident DeepSeek rows on GB10. Keep GLM, streaming and multi-GPU dispatch unchanged. Test overlapping experts, distinct gate/up weights, invalid IDs and exact agreement with separate rows; CUDA memory, race and synchronization checks pass.
2026-09-06 00:40:24 +02:00
Salvatore Sanfilippo b42682f12f Reuse aligned Q8 scratch during CUDA decoding
Avoid per-call pool allocations in dense and paired aligned Q8 kernels. Reuse the existing device-checked buffer, retaining the pool fallback for missing or undersized scratch.

Three interleaved Spark Flash Q2 runs improve 2K/4K/8K steady decode from 17.90/15.23/15.01 to 19.25/16.22/15.97 t/s. Prefill is unchanged and full prefill and post-decode logits match exactly. Add scratch fallback and graph replay tests.
2026-09-05 20:36:08 +02:00
Salvatore Sanfilippo 9d9e1296d2 Budget ROCm allocations against usable pinned memory
Exclude CMA pages from host availability, guard pinned and integrated-GPU allocations, and reserve space for the OS and required runtime buffers. Defer optional Q8 expansion and avoid wasting large model arenas.

Add memory parsing and allocation-admission tests. Focused Strix checks cover matched Flash/DSpark, resident GLM and automatic, oversized and one-expert SSD cache budgets.
2026-09-05 19:41:28 +02:00
antirez f9c459ce2f Fix ROCm MMQ scratch lifetime and tail reads 2026-09-01 03:26:23 +02:00
antirez 4b321cf1ec Make ROCm release builds warning-free 2026-08-31 15:12:02 +02:00
antirez a547fdff4a Merge pull request #887 from kyuz0/perf/rocm-gfx1151-mmq-kernel-lab
# Conflicts:
#	Makefile
#	ds4.c
#	ds4_bench.c
#	ds4_help.c
#	tests/test_gpu_args_cli.sh
2026-08-31 11:48:21 +02:00
kyuz0 c012d5cedf fix(rocm): stabilize gfx1151 MMQ routing maps 2026-08-29 21:51:45 +01:00
Donato Capitella e532136631 fix(rocm): adapt DSpark scheduling on gfx1151 2026-08-29 21:51:45 +01:00
Donato Capitella 227fa190aa perf(rocm): accelerate gfx1151 DSpark verification 2026-08-29 21:51:45 +01:00
Donato Capitella ab3346a695 bench: finalize gfx1151 prefill result 2026-08-29 21:51:45 +01:00
Donato Capitella 1ef0680b79 perf(rocm): default to tuned gfx1151 prefill paths 2026-08-29 21:51:45 +01:00
Donato Capitella 491e7e3d3f perf(rocm): remove rejected paired IQ2 kernel 2026-08-29 21:51:45 +01:00
Donato Capitella c40e8a8e09 perf(rocm): pair IQ2 gate and up tiles 2026-08-29 21:51:45 +01:00
Donato Capitella 4bf7c47b71 perf(rocm): compact IQ2 MoE tile launches 2026-08-29 21:51:45 +01:00
Donato Capitella 9ab922f50e perf(rocm): tighten IQ2 MoE launch bound 2026-08-29 21:51:45 +01:00
kyuz0 0610a6577e rocm: use cached IQ2 sign masks in MMQ 2026-08-29 21:51:44 +01:00
kyuz0 9933e01f50 rocm: wire tuned MMQ IQ2 prefill experiment 2026-08-29 21:51:44 +01:00
kyuz0 61e9b991c3 rocm: add gfx1151 MMQ kernel lab 2026-08-29 21:51:44 +01:00
antirez 147109a3cc Add GLM 5.3 Flash inference
Implement GLM 5.3 Q2 and Q4 inference across Metal and CUDA, including tensor parallelism, RDMA, batching, MTP, snapshots, SSD streaming, and GLM 5.2 shared-path improvements.

Add quantization and validation tools, official quality fixtures, model downloads, regression coverage, release QA, and user documentation.
2026-08-28 23:26:29 +02:00
antirez 67d97ab48d Add native MXFP4 inference to CUDA 2026-08-03 13:13:50 +02:00
antirez 73dd0f9004 cuda: fix generic MMQ linkage and warnings 2026-08-03 00:01:55 +02:00
Entrpi 3b3b29eb3c cuda: build and route aligned self-load artifacts 2026-08-02 23:48:38 +02:00
EntrpiandClaude Fable 5 0f62c620e8 cuda: vendored mmq prefill tier (raw entries) from batched-serving fork
Vendors the Entrpi/ds4 fork's cuda/mmq module at its v0.5.1 state
(llama.cpp mmq kernels pinned in cuda/mmq/VENDOR.md, MIT, plus the
fork's ds4_mmq C ABI, D2R kernels and repack library; fused prefill
pipeline portions carry Marco Palaferri's Portions-Copyright headers)
and wires the RAW-layout tier only: dense Q8_0 GEMMs and the IQ2_XXS
gate/up pair + Q2_K down routed-MoE pipeline at n_tok >= 2. The
aligned-SoA / D2R / producer-quantized tiers and the weight server are
deliberately not wired (they need the repack artifact pipeline).
Decode (n_tok == 1) is untouched. mmq changes FP32 reduction order vs
the cublas+dequant pipeline, so prefill logits drift at ULP scale:
gated on quality mode off, DS4_CUDA_MMQ=0 restores legacy dispatch.

Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_011CsqQzZEeuz9biUSEkGm8b
2026-08-02 00:47:10 +02:00